Customer Focused R&D
AMD uses a differentiated approach to submicron process technology research and development that is efficient, practical and highly effective. This approach results in AMD’s continued leadership in product performance-per-watt, combined with consistently high wafer yields using many of today’s most advanced submicron technologies.

AMD Strained Silicon Technologies
Strained Silicon increases transistor performance by enhancing the transport properties of the electrical charge carriers in the channel region of the transistor. Electrons (or holes) can “transport” more quickly through the transistor, thereby improving overall performance without increasing leakage and therefore power.

• AMD Second-Generation Stained Silicon: In December 2004, AMD and IBM revealed a breakthrough called “dual stress liners” that involves a new method of simultaneously straining both N-channel and P-channel transistors (the primary components of today’s digital integrated circuits) to deliver processors with increasing levels of performance, and at power levels consistent with or lower than former chips.

• AMD Third-Generation Strained Silicon in Production at 65nm: In December 2005, AMD unveiled its third-generation strained silicon technologies, which were jointly developed with IBM and now in use on AMD’s advanced 65nm products.

• AMD Fourth-Generation Strained Silicon for 45nm: In December 2006, AMD and IBM presented fourth-generation strain technology and set records for the highest CMOS performance up to that point in a 45nm process technology.

AMD Silicon-On-Insulator (SOI) Technologies
AMD chose to use advanced SOI transistors starting with its eighth-generation designs. By using these faster, yet cooler, transistors, AMD continues to deliver higher-performance processors that operate at lower wattage levels and generate less heat than would otherwise be possible using standard bulk silicon.

Ultra-Low-K Dielectrics
In December 2006, IBM and AMD presented joint work on the use of ultra-low-K interconnect dielectrics and multiple enhanced transistor strain techniques for application to the 45nm microprocessor process generation. The addition of ultra-low-K interconnect provides a 15 percent reduction in wiring-related delay as compared to conventional low-K dielectrics.

Immersion Lithography
AMD’s 45nm strategy calls for the use of immersion lithography to produce increasingly complex designs at finer geometries and enhanced chip-level performance. Immersion lithography provides increased depth of focus and improved image fidelity that can improve chip-level performance and manufacturing efficiency.

High-K Metal Gates
Many of the traditional materials used in semiconductor manufacturing have started to reach physical limits in how much more they can be scaled smaller or thinner without sacrificing transistor power consumption or performance.  For example, at the gate of the transistor, new high-k dielectrics can increase capacitance (higher capacitance = higher drive current and higher performance) without increasing leakage current at the very thin dimensions. The addition of metal gates, along with high-K, provides AMD with an additional tool to further improve performance and power efficiency within the 45nm or 32nm node generations, depending on when it is needed to meet customer requirements.

AMD and IBM, strategic partners, collaborate to develop the latest advancements in High-K Metal Gate technology.
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